The present invention relates to semiconductor integrated circuit devices, and in particular to semiconductor integrated circuit devices having DRAMs (Dynamic Random Access Memories) and a method of manufacturing them.
A semiconductor integrated circuit device having a DRAM is described, for example, in Japanese Patent Application No. 7-208037 filed in the name of the assignee of the present application on Aug. 15, 1995, in which a DRAM is disclosed having a so-called capacitor-over-bit line structure, i.e., having a structure such that memory cell capacitors are provided over bit lines.
In that technique, cap insulating films and side walls covering word lines and bit lines are made of a silicon nitride so that capacitor contact holes through which capacitors and semiconductor regions of memory cell selection MOS FETs are connected and bit line contact holes through which bit lines and semiconductor regions of memory cell selection MOS FETs are connected can be formed in self-alignment to thereby improve the accuracy of alignment of the contact holes and reduce the contact hole diameters with a result that the memory cell size can be decreased.
Meanwhile, in the recent years, it is more and more expected for DRAMs to have device elements highly integrated with fine patterning process margin sufficiently preserved and to have enhanced performance characteristics. To this end, it is now considered essential to form capacitor contact holes and bit line contact holes in self-alignment for reduction of memory cell size and how to effectively reduce unnecessary stray capacity accompanying the bit lines.
The present invention relates to the subject matter of U.S. patent application Ser. No. 08/694,766 filed on Aug. 9, 1996 (corresponding to Korean Patent Application No. 33,141/96 filed on Aug. 9, 1996 and to Taiwanese Patent Application No. 84109019 filed on Aug. 29, 1995), the whole of the disclosure of which is herein incorporated by reference. That application corresponds to the above-mentioned Japanse Patent Application No. 7-208037.
An object of the present invention is to provide a technique for reducing the bit line stray capacity in a semiconductor integrated circuit device having a memory device.
Another object of the present invention is to provide a technique for alleviating alignment accuracy requirement for capacitor contact holes and bit line contact holes for memory cell size reduction and for reducing bit line stray capacity.
According to one aspect of the present invention, in a semiconductor integrated circuit device with a memory device, the memory device including first conductors each having its upper and side surfaces covered with a first insulating film, second conductors provided so as to be transverse to and insulated from the first conductors and covered with a second insulating film, and a plurality of memory cells each provided at one of intersections between the first and second conductors and having a capacitor and a memory cell selection transistor, contact holes for connecting semiconductor regions of the transistors and the capacitors and contact holes for connecting bit lines and semiconductor regions of the transistors are formed in self-alingment, and the second insulating film has a permittivity smaller than that of the first insulating film.
The second insulating film may be made of a material having a permittivity substantially equal to that of the first insulating film. In that case, the second insulating film should be formed to a thickness larger than the first insulating film.